This disclosure relates to using multiple lock-detect circuitries with one or more phase locked loop (PLL) circuitries.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
Many electrical devices, such as mobile phones, computers, automotive electronic, communication systems, and industrial machinery among others, employ digital data processing circuitry that may operate according to clock signals. In many cases, the clock signals are provided to the digital data processing circuitry by phase-locked loop (PLL) modules. PLL modules are circuitry that provide stable and accurate clock signals by receiving an input clock signal from some clock source (e.g., a serial data signal) and outputting a stabilized clock signal that may be used for synchronization of the digital data processing circuitry. In basic terms, a PLL module may detect and synchronize the phases of an input clock signal and the phases of the output clock signal, resulting in a stable output clock signal. If the output clock signal reaches an acceptable level of stability, it may be considered locked.
Parts of an electrical device that receive clock signals from a PLL may benefit from receiving information related to whether the clock signal from the PLL is locked. In some systems, specialized lock-detect circuitry may be responsible for identifying whether the clock signal from the PLL is locked. The specialized lock-detect circuitry may occupy a region of the circuit which may be a constrained resource in some systems.